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HD74AC112

Renesas
Part Number HD74AC112
Manufacturer Renesas
Description Dual JK Negative Edge-Triggered Flip-Flop
Published Dec 4, 2017
Detailed Description HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop REJ03D0244–0200Z (Previous ADE-205-364 (Z)) Rev.2.00 Jul...
Datasheet PDF File HD74AC112 PDF File

HD74AC112
HD74AC112

Overview
HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop REJ03D0244–0200Z (Previous ADE-205-364 (Z)) Rev.
2.
00 Jul.
16.
2004 Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop.
When the clock goes High, the inputs are enabled and data will be accepted.
The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed.
Input data is transferred to the outputs on the falling edge of the clock pulse.
Features • Outputs Source/Sink 24 mA • HD74ACT112 has TTL-Compatible Inputs • Ordering Information: Ex.
HD74AC112 Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC112FPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel) HD74AC112RPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel) Notes: 1.
Please consult the sales office for the abo...


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