74AUP1G175 Low-power D-type flip-flop with reset; positive-edge trigger Rev.
7 — 18 January 2022 Product data sheet 1.
General description The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output.
The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.
A LOW on MR causes the flip-flop and output to be reset to LOW.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures very low static and dynamic power consumption across the entire VCC r...

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