DS32EL0124, DS32ELX0124 www.
ti.
com SNLS284K – MAY 2008 – REVISED APRIL 2013 DS32EL0124 , DS32ELX0124 125 MHz - 312.
5 MHz FPGA-Link Deserializer with DDR LVDS Parallel Interface Check for Samples: DS32EL0124, DS32ELX0124 FEATURES 1 •2 5-bit DDR LVDS Parallel Data Interface • Programmable Receive Equalization • Selectable DC-Balance Decoder • Selectable De-Scrambler • Remote Sense for Automatic Detection and Negotiation of Link Status • No External Receiver Reference Clock Required • LVDS Parallel Interface • Programmable LVDS Output Clock Delay • Supports Output Data-Valid Signaling • Supports Keep-Alive Clock Output • On Chip LC VCOs • Redundant Serial Input (ELX device only) • Retimed S...

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