CY28343 Zero Delay SDR/DDR Clock Buffer Features • Phase-lock loop clock distribution for DDR and SDR SDRAM applications • One-single-end clock input to 6 pairs DDR outputs or 13 SDR outputs.
• External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for SDR.
Table 1.
Function Table SELDDR_SDR# 1= DDR Mode CLKIN 2.
5V Compatible 3.
3V Compatible SDRAM(0:12) OFF DDRT/C(0:5) Active 2.
5V Compatible OFF FBIN_DDR 2.
5V Compatible OFF FBOUT_DDR Active 2.
5V Compatible OFF FBIN_SDR FBOUT_SDR OFF OFF • External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for DDR.
• SMBus interface enables/disables outputs.
• Conforms to...

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