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CY28341

Part Number	CY28341
Manufacturer	Cypress Semiconductor
Description	Universal Single-Chip Clock Solution
Published	Jun 8, 2007
Detailed Description	CY28341 Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems Features • • • • • Supports VIA P4M266/K...
Datasheet	CY28341 PDF File

Overview

CY28341 Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems Features • • • • • Supports VIA P4M266/KM266 chipsets Supports Pentium® 4, Athlon™ processors Supports two DDR DIMMS Supports three SDRAMS DIMMS at 100 MHz Provides: — Two different programmable CPU clock pairs — Six differential SDRAM DDR pairs — Three low-skew/low-jitter AGP clocks — Seven low-skew/low-jitter PCI clocks — One 48M output for USB — One programmable 24M or 48M for SIO • Dial-a-Frequency™ and Dial-a-dB features • Spread Spectrum for best electromagnetic interference (EMI) reduction • Watchdog feature for systems recovery • SMBus-compatible for programmability • 56-pin SSOP and TSSOP packages Table 1.
Frequency Selection Table FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1100 1111 CPU 66.
80 100.
00 120.
00 133.
33 72.
00 105.
00 160.
00 140.
00 77.
00 110.
00 180.
00 150.
00 90.
00 100.
00 200.
00 133.
33 AGP 66.
80 66.
80 60.
00 66.
67 72.
00 70.
00 64.
00 70.
00 77.
00 73.
33 60.
00 60.
00 60.
00 66.
67 66.
67 66.
67 PCI 33.
40 33.
40 30.
00 33.
33 36.
00 35.
00 32.
00 35.
00 38.
50 36.
67 30.
00 30.
00 30.
00 33.
33 33.
33 33.
33 Block Diagram www.
DataSheet4U.
com Pin Configuration[1] VDDR REF(0:1) REF0 VDDI CPUCS_T/C FS0 XIN XOUT XTAL SELP4_K7# VDDC CPU(0:1)/CPU0D_T/C VDDPCI FS2 PLL1 FS3 FS1 PCI(3:6) PCI_F MULTSEL PCI2 PCI1 VDDAGP AGP(0:2) VDD48M 48M /2 PD# SDATA SCLK SMBus PLL2 WDEN 24_48M WD SELSDR_DDR Buf_IN S2D CONVERT SRESET# VDDD FBOUT DDRT(0:5)/SDRAM(0,2,4,6,8,10) DDRC(0:5)/SDRAM(1,3,5,7,9,11) *FS0/REF0 VSSR XIN XOUT VDDAGP AGP0 *SELP4_K7/AGP1 AGP2 VSSAGP **FS1/PCI_F **SELSDR_DDR/PCI1 *MULTSEL/PCI2 VSSPCI PCI3 PCI4 VDDPCI PCI5 PCI6 VSS48M **FS3/48M **FS2/24_48M VDD48M VDD VSS IREF *PD#/SRESET# SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VTTPWRGD#/REF1 VDDR VSSC CPUT/CPUOD_T CPUC/CPUOD_C VDDC VDDI CPUCS_C CPUCS_T VSSI FBOUT BUF_IN DDRT...

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