74LS42

74LS40 : SN54/74LS40 DUAL 4-INPUT NAND BUFFER DUAL 4-INPUT NAND BUFFER VCC 14 13 12 11 10 9 8 LOW POWER SCHOTTKY 1 2 3 4 5 6 7 GND 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 N SUFFIX PLASTIC CASE 646-06 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current — High Output Current — Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 – 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 – 1.2 12 24 Unit V °C mA mA FAST AND LS TTL DATA 5-51 SN54/74LS40 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limi.

74LS42 : The LS42 decoder accepts four active HIGH BCD inputs and provides ten mutually exclusive active LOW outputs, as shown by logic symbol or diagram. The active LOW outputs facilitate addressing other MSI units with LOW input enables. The logic design of the LS42 ensures that all outputs are HIGH when binary codes greater than nine are applied to the inputs. The most significant input A3 produces a useful inhibit function when the LS42 is used as a one-of-eight decoder. The A3 input can also be used as the Data input in an 8-output demultiplexer application. TRUTH TABLE A0 L H L H L H L H L H L H L H L H A1 L L H H L L H H L L H H L L H H A2 L L L L H H H H L L L L H H H H A3 L L L L L L L L H .

74LS42 : Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 – 0.30 1.15 0° – 8° + 0.20 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.70 ± 0.20 0.15 0.12 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g *Dimension including the plating thickness Base material dimension Unit: mm 8.65 9.05 Max 14 8 3.95 1 1.75 Max 7 *0.20 ± 0.05 6.10 – 0.30 1.08 + 0.10 0.635 Max 0° – 8° 0.67 0.60 + – 0.20 1.27 *0.4.

74LS43 : .

74LS466 : www.DataSheet4U.com SN54LS465 THRU SN54LS468, SN74LS465 THRU SN74LS468 OCTAL BUFFERS WITH 3-STATE OUTPUTS SDLS179 – JANUARY 1981 – REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1988, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 www.DataSheet4U.com SN54LS465 THRU SN54LS468, SN74LS465 THRU SN74LS468 OCTAL BUFFERS WITH 3-STATE OUTPUTS SDLS179 – JANUARY 1981 – REVISED MARCH 1988 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 www.DataSheet4.

74LS47 : BCD TO 7-SEGMENT DECODER/DRIVER The SN54 / 74LS47 are Low Power Schottky BCD to 7-Segment Decoder / Drivers consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. They offer active LOW, high sink current outputs for driving indicators directly. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available to the seven decoding AND-OR-INVERT gates. The remaining NAND gate and three input buffers provide lamp test, blanking input / ripple-blanking output and ripple-blanking input. The circuits accept 4-bit binary-coded-decimal (BCD) and, depending on the state of the auxiliary inputs, decodes this data to drive a 7-segment display indicato.

74LS47 : SN74LS47 BCD to 7-Segment Decoder/Driver The SN74LS47 are Low Power Schottky BCD to 7-Segment Decoder/ Drivers consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. They offer active LOW, high sink current outputs for driving indicators directly. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available to the seven decoding AND-OR-INVERT gates. The remaining NAND gate and three input buffers provide lamp test, blanking input / ripple-blanking output and ripple-blanking input. The circuits accept 4-bit binary-coded-decimal (BCD) and, depending on the state of the auxiliary inputs, decodes this data to drive a 7-segment display indi.

74LS47 : 74LS47 BCD-TO-SEVEN SEGMENT DECORDER/DRIVER Function Table .

74LS47 : The DM74LS47 accepts four lines of BCD (8421) input data, generates their complements internally and decodes the data with seven AND/OR gates having open-collector outputs to drive indicator segments directly. Each segment output is guaranteed to sink 24 mA in the ON (LOW) state and withstand 15V in the OFF (HIGH) state with a maximum leakage current of 250 µA. Auxiliary inputs provided blanking, lamp test and cascadable zero-suppression functions. Features s Open-collector outputs s Drive indicator segments directly s Cascadable zero-suppression capability s Lamp test input Ordering Code: Order Number DM74LS47M DM74LS47N Package Number M16A N16E Package Description 16-Lead Small Outline I.

74LS471 : www.DataSheet4U.com .

74LS48 : Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) DP-14 Conforms Conforms 0.97 g Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 – 0.30 1.15 0° – 8° + 0.20 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.70 ± 0.20 0.15 0.12 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g *Dimension including the plating thickness Base material dimension Unit: mm 8.65 9.05 Max 14 8 3.95 1 1.75 Max 7 *0.20 ± 0.05 6.10 – 0.30 1.08 + 0.10 0.635 Max 0° – 8° 0.67 0.60 + – 0.20 1.27 *0.4.

74LS48 : SN54/74LS48 BCD TO 7-SEGMENT DECODER The SN54 / 74LS48 is a BCD to 7-Segment Decoder consisting of NAND gates, input buffers and seven AND-OR-INVERT gates. Seven NAND gates and one driver are connected in pairs to make BCD data and its complement available to the seven decoding AND-OR-INVERT gates. The remaining NAND gate and three input buffers provide lamp test, blanking input/rippleblanking input for the LS48. The circuit accepts 4-bit binary-coded-decimal (BCD) and, depending on the state of the auxiliary inputs, decodes this data to drive other components. The relative positive logic output levels, as well as conditions required at the auxiliary inputs, are shown in the truth tables. Th.

74LS48 : The ’LS48 translates four lines of BCD (8421) input data into the 7-segment numeral code and provides seven corresponding outputs having pull-up resistors as opposed to totem pole pull-ups These outputs can serve as logic signals with a HIGH output corresponding to a lighted lamp segment or can provide a 1 3 mA base current to npn lamp driver transistors Auxiliary inputs provide lamp test blanking and cascadable zero-suppression functions The ’LS48 decodes the input data in the pattern indicated in the Truth Table and the segment identification illustration Connection Diagram Dual-In-Line Package TL F 10172 – 1 Order Number DM74LS48M or DM74LS48N See NS Package Number M16A or N16E C1995 .

74LS49 : Unit: mm 10.06 10.5 Max 14 8 5.5 1 7 *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 7.80 – 0.30 1.15 0° – 8° + 0.20 1.42 Max 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.70 ± 0.20 0.15 0.12 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DA — Conforms 0.23 g *Dimension including the plating thickness Base material dimension Unit: mm 8.65 9.05 Max 14 8 3.95 1 1.75 Max 7 *0.20 ± 0.05 6.10 – 0.30 1.08 + 0.10 0.635 Max 0° – 8° 0.67 0.60 + – 0.20 1.27 *0.40 ± 0.06 0.11 0.14 + – 0.04 0.15 0.25 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-14DN Conforms Conforms 0.13 g *Pd plating Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third pa.

74LS49 : SN54/74LS490 DUAL DECADE COUNTER The SN54 / 74LS490 contains a pair of high-speed 4-stage ripple counters. Each half of the SN54 / 74LS490 has individual Clock, Master Reset and Master Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code. • • • • Dual Version of SN54 / 74LS490 Individual Asynchronous Clear and Preset to 9 for Each Counter Count Frequency — Typically 65 MHz Input Clamp Diodes Limit High-Speed Termination Effects DUAL DECADE COUNTER LOW POWER SCHOTTKY CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 CPb 15 MRb 14 Q0b 13 MSb 12 Q1b 11 Q2b 10 Q3b 9 16 1 J SUFFIX CERAMIC CASE 620-09 1 CPa 2 MRa 3 Q0a 4 MSa 5 Q1a 6 Q2a 7 Q3a 8 GND 16 1 N SUFFIX PLASTIC CASE .