Part Number
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TH58100FTI |
Manufacturer
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Toshiba Semiconductor |
Description
|
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS |
Published
|
Dec 21, 2005 |
Detailed Description
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TH58100FTI
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2
1-GBIT (128M × 8 BITS) CMOS NAND E PROM...
|
Datasheet
|
TH58100FTI
|
Overview
TH58100FTI
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2
1-GBIT (128M × 8 BITS) CMOS NAND E PROM DESCRIPTION
The TH58100 is a single 3.
3 V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks.
The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments.
The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes × 32 pages).
The TH58100 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as we...
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