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TH58100FTI

Part Number	TH58100FTI
Manufacturer	Toshiba Semiconductor
Description	TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
Published	Dec 21, 2005
Detailed Description	TH58100FTI TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 1-GBIT (128M × 8 BITS) CMOS NAND E PROM...
Datasheet	TH58100FTI PDF File

Overview

TH58100FTI TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 1-GBIT (128M × 8 BITS) CMOS NAND E PROM DESCRIPTION The TH58100 is a single 3.
3 V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks.
The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments.
The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes × 32 pages).
The TH58100 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.
The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage.
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TH58100FT TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS - Toshiba Semiconductor
TH58100FTI TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS - Toshiba Semiconductor

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