FEATURES • • • • • • • • w w Full CMOS output swing with 40-mA output drive capability.
25-mA output drive at TTL level.
Advanced, low power, sub-micron CMOS processes.
25MHz fundamental crystal or clock input.
Two outputs fixed at 125MHz.
.
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.
3V operation.
Available in 8-Pin 150mil SOIC.
w .
D at h S a t e e 4U .
m o c PRELIMINARY PLL650-10 Network LAN Clock for Gigabit Ethernet PIN CONFIGURATION XIN XOUT GND 125MHz 1 2 3 4 8 7 6 5 VDD GND VDD 125MHz P LL 650-10 DESCRIPTIONS The PLL 650-10 is a low cost, low jitter, and high performance clock synthesizer.
With PhaseLink’s proprietary analog Phase Locked Lo...

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