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PLL650-04

PhaseLink
Part Number PLL650-04
Manufacturer PhaseLink
Description Low EMI Clock
Published Feb 10, 2006
Detailed Description m Preliminary PLL650-04 o c . EMI Clock for 10/100 PHY and Gigabit Ethernet Low U t4 e FEATURES PIN CONFIGURATION e hswi...
Datasheet PDF File PLL650-04 PDF File

PLL650-04
PLL650-04

Overview
m Preliminary PLL650-04 o c .
EMI Clock for 10/100 PHY and Gigabit Ethernet Low U t4 e FEATURES PIN CONFIGURATION e hswing with 25-mA output drive • Full CMOS output S capability at TTL level.
a t • Advanced, low power, sub-micron CMOS processes.
a • 25 MHz .
D fundamental crystal or clock input.
• Low jitter (< 80ps cycle-to-cycle) w • 25 MHz and 50 MHz outputs w CLKOUT selectable between 90, 100, 125, 133, w• Five 145 and 150 MHz.
XIN 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 VDD XOUT/SSTE*^ GND 50M_EN^ 25MHz/25M_EN*^ GND PLL 650-04 VDD • • • • • • SSTE (SST Enable) Low EMI selector for CLKOUT.
Output enable functionality.
Zero PPM synthesis error in all clocks.
Ideal for Network switches.
3.
3V operation.
Available in 20-Pin 150mil SSOP.
DESCRIPTION The PLL 650-04 is a low cost, low jitter, and high performance clock synthesizer.
With PhaseLink proprietary analog Phase Locked Loop techniques, the chip accepts 25.
0 MHz crystal, and produces multiple output clocks for networking chips.
A CLKOUT signal of selectable frequency (25MHz, 48MHz, 50MHz, 90MHz, 100MHz, 125MHz, 133MHz, 145MHz or 150 MHz) is available at 5 output pins.
Through an SST enable (SSTE) selector, the CLKOUT signal can be modulated to reduce EMI through Spread Spectrum Technology.
Output enable selectors are available to enable/disable the output signals.
BLOCK DIAGRAM XIN XOUT XTAL OSC m o .
c U 4 t e e h S a t a .
D w w w VDD CLKOUTº CLKOUTº FS1^ CLKOUTº 10 11 CLKOUT_EN^ 50MHz GND CLKOUTº FS0 CLKOUTº GND Note: ^: Internal pull-up resistor *: Bi-directional pin º: Low EMI output SELECTION TABLE FS1 0 0 0 1 1 1 FS0 0 M 1 0 M 1 CLKOUT 90 MHz 100 MHz 125 MHz 133 MHz 145 MHz 150 MHz SSTE 0 1 SST MODULATION ± 0.
25% Center spread OFF Tri-level input pins: 0 = connect to GND M= not connected, 1 = connect to VDD 25M_EN (enable) 25MHz 1 50M_EN (enable) 50MHz FS (0:1) Control Logic 1 CLKOUT_EN (enable) SSTE (SST enable) 5 CLKOUT (90 100, 125, 133, 145 or 150 MHz) 47745 Fremont B...


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