com PRELIMINARY INFORMATION ICS571 Low Phase Noise Zero Delay Buffer Features • Packaged in 8 pin SOIC.
• Can function as low phase noise x2 multiplier.
• Low skew outputs.
One is ÷2 of other.
• Input clock frequency up to 160 MHz at 3.
3V.
• Phase noise of better than -100 dBc/Hz from 1kHz to 1MHz offset from carrier • Can recover poor input clock duty cycle.
• Output clock duty cycle of 45/55 at 3.
3V.
• High drive strength for 100 MHz outputs.
• Full CMOS clock swings with 25mA drive capability at TTL levels.
• Advanced, low power CMOS process.
• Operating voltages of 3.
0 to 5.
5 V.
Description The ICS571 is a high speed, high output drive, low phase noise Zero Delay Buff...

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