www.
DataSheet4U.
com Port Bypass Circuits for Fibre Channel Arbitrated Loop Standard and its Extensions Technical Data Features • Supports ANSI X3T11 1.
0625 Gbps FC-AL Loop Configuration • Supports 802.
3z 1.
25 Gbps Gigabit Ethernet (GE) Rates • Single PBC, CDR, Dual Signal Detect (SD) in a Single Package • Bidirectional, Symmetric Bypass Capability • CDR in Bypass Path and Loop Path • CDR Location Determined by Wiring Configuration of Pins on PCB (Patent Pending) • Envelope Detect on Cable Input (SD) for Both Directions • Equalizers On All Inputs • High Speed PECL I/Os Referenced to VCC • Buffered Line Logic (BLL) Outputs without External Bias Resistors • 0.
4 W Typical Power at VCC = 3.
3 V •...

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