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HDMP-0421

Part Number	HDMP-0421
Manufacturer	Hewlett-Packard
Description	Port Bypass Circuits
Published	Dec 28, 2006
Detailed Description	www.DataSheet4U.com Port Bypass Circuits for Fibre Channel Arbitrated Loop Standard and its Extensions Technical Data F...
Datasheet	HDMP-0421 PDF File

Overview

www.
DataSheet4U.
com Port Bypass Circuits for Fibre Channel Arbitrated Loop Standard and its Extensions Technical Data Features • Supports ANSI X3T11 1.
0625 Gbps FC-AL Loop Configuration • Supports 802.
3z 1.
25 Gbps Gigabit Ethernet (GE) Rates • Single PBC, CDR, Dual Signal Detect (SD) in a Single Package • Bidirectional, Symmetric Bypass Capability • CDR in Bypass Path and Loop Path • CDR Location Determined by Wiring Configuration of Pins on PCB (Patent Pending) • Envelope Detect on Cable Input (SD) for Both Directions • Equalizers On All Inputs • High Speed PECL I/Os Referenced to VCC • Buffered Line Logic (BLL) Outputs without External Bias Resistors • 0.
4 W Typical Power at VCC = 3.
3 V • 5 V Tolerant LVTTL I/O • 24 Pin SSOP Package HDMP-0421 Single PBC & CDR Description The HDMP-0421 is a Single Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR), and dual Signal Detect (SD) capability.
This configuration will control jitter accumulation while repeating incoming signals.
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