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com 3 V LVDS Quad CMOS Differential Line Receiver ADN4668 FUNCTIONAL BLOCK DIAGRAM VCC FEATURES ±15 kV ESD protection on receiver input pins 400 Mbps (200 MHz) switching rates Flow-through pin configuration simplifies PCB layout 150 ps channel-to-channel skew (typical) 100 ps differential skew (typical) 2.
7 ns maximum propagation delay 3.
3 V power supply High impedance outputs on power-down Low power design (3 mW quiescent typical) Interoperable with existing 5 V LVDS drivers Accepts small swing (310 mV typical) differential input signal levels Supports open, short, and terminated input fail-safe 0 V to −100 mV threshold region Conforms to TIA/EIA-644 LVDS standard Industri...

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