FEATURES ±15 kV ESD protection on output pins 600 Mbps (300 MHz) switching rates Flow-through pinout simplifies PCB layout 300 ps typical differential skew 700 ps maximum differential skew 1.
5 ns maximum propagation delay 3.
3 V power supply ±355 mV differential signaling Low power dissipation: 23 mW typical Interoperable with existing 5 V LVDS receivers Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range (−40°C to +85°C) Available in surface-mount (SOIC) package APPLICATIONS Backplane data transmission Cable data transmission Clock distribution GENERAL DESCRIPTION The ADN4663 is a dual, CMOS, low voltage differential signaling (LVDS) line driver offering data rates o...

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