Part Number
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CY7C1373D |
Manufacturer
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Cypress Semiconductor |
Description
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18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM |
Published
|
Mar 12, 2010 |
Detailed Description
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CY7C1371D CY7C1373D
18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 1...
|
Datasheet
|
CY7C1373D
|
Overview
CY7C1371D CY7C1373D
18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture
Features
■ No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
■ Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock
■ Pin-compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need
to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.
3 V/2.
5 V I/O power supply (VDDQ) ■ Fast clock-to-output times
❐ 6.
5 ns (for 133-MHz device) ■ Clock enable (CEN) pin to ...
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