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DataSheet4U.
com ‡ 300 MHz 16-bit +LJK 'HQVLW\ )RXU /RZ6NHZ 'LVWULEXWHG 1HWZRUNV ‡ Two array clock/control networks available ‡ 6,000 Usable PLD Gates with 82 I/Os Counters, 400 MHz Datapaths ‡ 0.
35 µm four-layer metal non-volatile CMOS process for smallest die sizes (DV\WR8VH  )DVW 'HYHORSPHQW &\FOHV ‡ 100% routable with 100% utilization and to the logic cell flip-flop clock, set and reset inputs — each driven by an input-only pin ‡ Two global clock/control networks available to the logic cell; F1, clock, set and reset inputs a...

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