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QL3012

Part Number	QL3012
Manufacturer	QuickLogic
Description	qASIC 3 FPGA
Published	Feb 10, 2006
Detailed Description	. U 4 QL3012 pASIC 3 FPGA Data Sheet t e e h S ••••• • 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance a ...
Datasheet	QL3012 PDF File

Overview

.
U 4 QL3012 pASIC 3 FPGA Data Sheet t e e h S ••••• • 12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance a t a and High Density Eight Low-Skew Distributed Device .
D Highlights w Networks w Two array clock/control networks available Performance & High Density wHigh to the logic cell flip-flop clock, set and reset 12,000 Usable PLD Gates with 118 I/Os • • • 300 MHz 16-bit Counters, m o c 400 MHz Datapaths • 0.
35 µm four-layer metal non-volatile CMOS process for smallest die sizes Easy to Use / Fast Development Cycles • 100% routable with 100% utilization and inputs — each driven by an input-only pin • Two global clock/control networks available to the logic cell; F1, clock set, reset inputs and the input, I/O register clock, reset, and enable inputs as well as the output enable control — each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback complete pin-out stability • Variable-grain logic cells provide high performance and 100% utilization • Comprehensive design tools include high quality Verilog/VHDL synthesis Advanced I/O Capabilities • Interfaces with both 3.
3 V and 5.
0 V devices • PCI compliant with 3.
3 V and 5.
0 V buses for -1/-2/-3/-4 speed grades • Full JTAG boundary scan • I/O Cells with individually controlled Registered Input Path and Output Enables Total of 118 I/O Pins • 110 bidirectional input/output pins, PCI-compliant for 5.
0 V and 3.
3 V buses for -1/-2/-3/-4 speed grades • Four High Drive input-only pins • Four High Drive input-only/distributed network pins w w w .
D t a S a e h High Performance • Input + logic cell + output total delays under 6 ns • Data path speeds over 400 MHz • Counter speeds over 300 MHz t e U 4 .
c m o Figure 1: 320 pASIC 3 Logic Cells © 2003 QuickLogic Corporation w w w .
D at h S a t e e 4U .
m o c www.
quicklogic.
com • • • • • • 1 QL3012 pASIC 3 FPGA Data Sheet Rev F Architecture Overview The QL3012 is a 12,000 usable PLD gate member of the pAS...

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