Part Number
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QL3004 |
Manufacturer
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QuickLogic Corporation |
Description
|
PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
Published
|
May 22, 2010 |
Detailed Description
|
QL3004 pASIC 3 FPGA Data Sheet
••••••
4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
De...
|
Datasheet
|
QL3004
|
Overview
QL3004 pASIC 3 FPGA Data Sheet
••••••
4,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Device Highlights
High Performance & High Density
• 4,000 Usable PLD Gates with 74 I/Os • 300 MHz 16-bit www.
DataSheet4U.
com
Eight Low-Skew Distributed Networks
• Two array clock/control networks available
Counters, 400 MHz Datapaths • 0.
35 µm four-layer metal non-volatile CMOS process for smallest die sizes
Easy to Use / Fast Development Cycles
• 100% routable with 100% utilization and
to the logic cell flip-flop clock, set and reset inputs — each driven by an input-only pin • Six global clock/control networks available to the logic cell; F1, clock set, reset inputs and ...
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