S T U/D428S
S amHop Microelectronics C orp.
Mar.
8,2007
N-C hannel Logic Level E nhancement Mode Field E ffect
Transistor
P R ODUC T S UMMAR Y
V DS S
40V
F E AT UR E S S uper high dense cell design for low R DS (ON ).
ID
50A
R DS (ON) ( m Ω ı ) T yp
8 @ V G S = 10V 10 @ V G S = 4.
5V
R ugged and reliable.
S urface Mount P ackage.
E S D P rotected.
D
D G S
G D
G
S
S TU S E R IE S TO-252AA(D-P AK)
S TD S E R IE S TO-251(l-P AK)
S
ABS OLUTE MAXIMUM R ATINGS (Ta=25 C unless otherwise noted)
Parameter Drain-Source Voltage Gate-Source Voltage Drain Current-Continuous @TC=25 C a -Pulsed Drain-Source Diode Forward Current Maximum Power Dissipation @Tc=25 C Symbol VDS VGS ID IDM IS PD TJ, TS...