Data Sheet
FEATURES
4 ADCs integrated into 1 package 98 mW ADC power per channel at 50 MSPS SNR = 73 dB (to Nyquist) ENOB = 12 bits SFDR = 84 dBc (to Nyquist) Excellent linearity
DNL = ±0.
5 LSB (typical) INL = ±1.
5 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.
3) Data and frame clock outputs 315 MHz full-power analog bandwidth 2 V p-p input
voltage range 1.
8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode
APPLICATIONS
Medical imaging and non...