ADSP-21160

ADSP-21161N : SUMMARY High performance 32-Bit DSP—applications in audio, medical, military, wireless communications, graphics, imaging, motor-control, and telephony Super Harvard Architecture—four independent buses for dual data fetch, instruction fetch, and nonintrusive zerooverhead I/O Code compatible with all other sharc family DSPs Single-instruction multiple-data (SIMD) computational archi- tecture—two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file Serial ports offer I2S support via 8 programmable and simultaneous receive or transmit pins, which support up to 16 transmit or 16 receive channels of audio SHARC Processor ADSP-21161N Integrated peri.

ADSP-21161 : ADSP-21161 SHARC® Processor Hardware Reference Revision 4.0, February 2005 Part Number 82-001944-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 Free Datasheet http://www.datasheet4u.net/ Copyright Information © 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent from Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringement of patents.

ADSP-21160N : SUMMARY High performance 32-bit DSP—applications in audio, medical, military, graphics, imaging, and communication Super Harvard architecture—4 independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead I/O Backward compatible—assembly source level compatible with code for ADSP-2106x DSPs Single-instruction, multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file Integrated peripherals—integrated I/O processor, 4M bits on-chip dual-ported SRAM, glueless multiprocessing features, and ports (serial, link, external bus, and JTAG) SHARC Digital Signal Processor ADSP-2.

ADSP-21160M : SUMMARY High performance 32-bit DSP—applications in audio, medical, military, graphics, imaging, and communication Super Harvard architecture—4 independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead I/O Backward compatible—assembly source level compatible with code for ADSP-2106x DSPs Single-instruction, multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file Integrated peripherals—integrated I/O processor, 4M bits on-chip dual-ported SRAM, glueless multiprocessing features, and ports (serial, link, external bus, and JTAG) SHARC Digital Signal Processor ADSP-2.