MC100EP196
3.
3V ECL Programmable Delay Chip with FTUNE
The MC100EP196 is a programmable delay chip (PDC) designed
primarily for clock deskewing and timing adjustment.
It provides variable
delay of a differential NECL/PECL input transition.
It has similar
architecture to the EP195 with the added feature of further tuneability in
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delay using the FTUNE pin.
The FTUNE input takes an analog
voltage
from VCC to VEE to fine tune the output delay from 0 to 60 ps.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2.
The delay increment
MARKING DIAGRAM*
of the EP196 has a digitally selectable resolution of ab...