m o .
c U 4 t e FEATURES e h • Full swing
CMOS S outputs with 25 mA drive capability a at TTL levels.
t 10-27MHz fundamental crystal or • Reference a clock.
.
D crystal load capacitor: no external • Integrated w load capacitor required.
w • Output clocks up to 160MHz at 3.
3V.
w• Low phase noise.
• • • • • Output Enable function tri-state outputs.
Low jitter: Less than 60 ps cycle to cycle.
Advanced, low power, sub-micron
CMOS process.
3.
3V operation.
Available in 16-Pin SOIC or TSSOP.
Preliminary
PLL601-01
Low Phase Noise PLL Clock Multiplier
PIN CONFIGURATION
CLK REFEN VDD VDD VDD
1 2
16 15
GND GND GND REFOUT OE S0 S3 S2
PLL 601-01
3 4 5 6 7 8
14 13 12 11 10 9
DESCRIPTIONS
The PLL...