INTEGRATED CIRCUITS DATA SHEET SAA7201 Integrated MPEG2 AVG decoder Objective specification File under Integrated Circuits, IC02 1997 Jan 29 Philips Semiconductors Objective specification Integrated MPEG2 AVG decoder FEATURES General • Uses single external Synchronous DRAM (SDRAM) organized as 1M × 16 interfacing at 81 MHz; compatible with the SDRAM ‘lite’ or ‘PC’ • Fast external CPU interface; 16-bit data + 8-bit address • Dedicated input for audio and video data in PES or ES format; data input rate: ≤9 Mbytes/s in byte mode; ≤20 Mbit/s in bit serial mode; audio and/or video data can also serve as input via CPU interface • Single 27 MHz external clock for time base reference and internal...

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