TMS626812A 1 048 576 BY 8ĆBIT BY 2ĆBANK SYNCHRONOUS DYNAMIC RANDOMĆACCESS MEMORY
SMOS691B − JULY 1997 − REVISED APRIL 1998
D Organization
1M Words × 8 Bits × 2 Banks
D 3.
3-V Power Supply (± 10% Tolerance) D Two Banks for On-Chip Interleaving
(Gapless Accesses)
D High Bandwidth − Up to 100-MHz Data
Rates
D CAS Latency (CL) Programmable to
2 or 3 Cycles From Column-Address Entry
D Burst Sequence Programmable to Serial or
Interleave
D Burst Length Programmable to 1, 2, 4, or 8 D Chip Select and Clock Enable for
Enhanced-System Interfacing
D Cycle-by-Cycle DQ-Bus Mask Capability D Auto-Refresh and Self-Refresh Capabilities D 4K Refresh (Total for Both Banks) D High-Speed, Low-Noise, Low-
Voltage...