DatasheetsPDF.com

MB9BF366N

Cypress Semiconductor
Part Number MB9BF366N
Manufacturer Cypress Semiconductor
Description Microcontroller
Published May 18, 2016
Detailed Description MB9B360R Series 32-Bit ARM® Cortex® - M4F FM4 Microcontroller The MB9B360R Series are a highly integrated 32-bit microc...
Datasheet PDF File MB9BF366N PDF File

MB9BF366N
MB9BF366N

Overview
MB9B360R Series 32-Bit ARM® Cortex® - M4F FM4 Microcontroller The MB9B360R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost.
These series are based on the ARM® Cortex®-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (USB, UART, CSIO, I2C, LIN).
Features 32-bit ARM® Cortex®-M4F Core Processor version: r2p1 Up to 160 MHz Frequency Operation FPU built-in Support DSP instruction Memory Protection Unit (MPU): improves the reliability of an embedded system Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels 24-bit System timer (Sys Tick): System timer for OS task management On-chip Memories [Flash memory] These series are based on two independent on-chip Flash memories.
MainFlash memory  Up to 1024 Kbytes  Built-in Flash Accelerator System with 16 Kbytes trace buffer memory  The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz.
Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System.
 Security function for code protection WorkFlash memory  32 Kbytes  Read cycle: • 6wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz • 4wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz • 2wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz • 0wait-cycle: the operation frequency up to 40MHz  Security function is shared with code protection [SRAM] This is composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2).
SRAM0 is connected to I-code bus or D-code bus of Cortex-M4F core.
SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core.
SRAM0: Up to 64 Kbytes SRAM1: Up to 32 Kbytes SRAM2: Up to 32 Kbytes External Bus...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)