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74HC4075-Q100

NXP
Part Number 74HC4075-Q100
Manufacturer NXP
Description Triple 3-input OR gate
Published Jun 1, 2016
Detailed Description 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate Rev. 1 — 22 May 2013 Product data sheet 1. General description Th...
Datasheet PDF File 74HC4075-Q100 PDF File

74HC4075-Q100
74HC4075-Q100

Overview
74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate Rev.
1 — 22 May 2013 Product data sheet 1.
General description The 74HC4075-Q100; 74HCT4075-Q100 is a triple 3-input OR gate.
Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2.
Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Complies with JEDEC standard JESD7A  Input levels:  For 74HC4075-Q100: CMOS level  For 74HCT4075-Q100: TTL level  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  Multiple package options 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range 74HC4075D-Q100 40 C to +125 C 74HCT4075D-Q100 74HC4075PW-Q100 40 C to +125 C 74HCT4075PW-Q100 Name SO14 TSSOP14 Description plastic small outline package; 14 leads; body width 3.
9 mm plastic thin shrink small outline package; 14 leads; body width 4.
4 mm Version SOT108-1 SOT402-1 NXP Semiconductors 74HC4075-Q100; 74HCT4075-Q100 Triple 3-input OR gate 4.
Functional diagram  $  %  &  $  %  &  $  %  & <  <  <  DDD Fig 1.
Logic symbol  •    •    •    DDD Fig 2.
IEC logic symbol 5.
Pinning information 5.
1 Pinning $ %< & DDD Fig 3.
Logic diagram (one gate) +&4 +&74 $  %  $  %  &  <  *1'   9&&  &  %  $  <  <  & DDD Fig 4.
Pin configuration SO14 +&4 +&74 $ % $ % & < *1'         9&&  &  %  $  <  <  & DDD Fig 5.
Pin configuration TSSOP14 5.
2 Pin description Table 2.
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