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IS61QDPB451236A

ISSI
Part Number IS61QDPB451236A
Manufacturer ISSI
Description 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM
Published Jun 10, 2016
Detailed Description IS61QDPB41M18A/A1/A2 IS61QDPB451236A/A1/A2 1Mx18, 512Kx36 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency)...
Datasheet PDF File IS61QDPB451236A PDF File

IS61QDPB451236A
IS61QDPB451236A

Overview
IS61QDPB41M18A/A1/A2 IS61QDPB451236A/A1/A2 1Mx18, 512Kx36 18Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.
5 Cycle Read Latency) NOVEMBER 2014 FEATURES DESCRIPTION  512Kx36 and 1Mx18 configuration available.
 On-chip Delay-Locked Loop (DLL) for wide data valid window.
 Separate independent read and write ports with concurrent read and write operations.
 Synchronous pipeline read with late write operation.
 Double Data Rate (DDR) interface for read and write input ports.
 2.
5 cycle read latency.
 Fixed 4-bit burst for read and write operations.
 Clock stop support.
The 18Mb IS61QDPB451236A/A1/A2 and IS61QDPB41M18A/A1/A2 are synchronous, highperformance CMOS static random access memory (SRAM) devices.
These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.
The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations...


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