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NB3N4666C

Part Number	NB3N4666C
Manufacturer	ON Semiconductor
Description	3.3 V Quad LVCMOS Differential Line Receiver Translator
Published	Jun 28, 2016
Detailed Description	NB3N4666C 3.3 V Quad LVCMOS Differential Line Receiver Translator Description The NB3N4666C is a quad−channel LVDS line...
Datasheet	NB3N4666C PDF File

Overview

NB3N4666C 3.
3 V Quad LVCMOS Differential Line Receiver Translator Description The NB3N4666C is a quad−channel LVDS line receiver/translator offering data rates up to 400 Mbps (200 MHz) and low power consumption.
The NB3N4666C receiver incorporates input fail−safe protection circuit that provides a known output voltage under input open−circuit, short and terminated (100 W) conditions.
The four independent inputs accept differential signals such as: M−LVDS, LVDS, LVPECL and HCSL and translates them to a single−ended, 3.
3 V LVCMOS.
The NB3N4666C also offers active high and active low enable/disable inputs (EN and EN) that allow users to control outputs of all four receivers.
These inputs enable or disable the receivers and switch the outputs to an active or high impedance state respectively (see Table 2).
The high impedance mode feature helps to reduce the quiescent power consumption to less than 10 mW typical, when the outputs of one or more NB3N4666C devices are multiplexed together.
Features • Accepts M−LVDS, LVDS, LVPECL and HCSL Differential Input Signal Levels • Maximum Data Rate of 400 Mbps • Maximum Clock Frequency of 200 MHz • 25 ps Typical Channel−to−Channel Skew • 3.
3 ns Maximum Propagation Delay • 3.
3 V ±10% Power Supply • High Impedance Outputs When Disabled ♦ Low Quiescent Power < 10 mW Typical • Supports Open, Short, and Terminated Input Fail−safe • −40°C to +85°C Ambient Operating Temperature • 16−Pin TSSOP, 5.
0 mm x 4.
4 mm x 1.
2 mm • These are Pb−Free Devices Applications • Point−to−point Data Transmission • Backplane Receivers • Clock Distribution Networks • Multidrop Buses www.
onsemi.
com 1 TSSOP−16 DT SUFFIX CASE 948F MARKING DIAGRAMS 16 NB3N 4666 ALYWG G 1 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) IN1 IN1 OUT1 EN NB3N4666C R1 R4 VCC IN4 IN4 OUT4 EN OUT2 OUT3 R2 R3 IN2 IN2 GND IN3 IN3 Figure 1.
Functional Block Diagram ORDERING INFORMATION See detailed orde...

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NB3N4666C 3.3 V Quad LVCMOS Differential Line Receiver Translator - ON Semiconductor

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