DatasheetsPDF.com

H5PS5162FFR-xxC

Hynix
Part Number H5PS5162FFR-xxC
Manufacturer Hynix
Description 512Mb DDR2 SDRAM
Published Jul 17, 2016
Detailed Description H5PS5162FFR Series 512Mb DDR2 SDRAM H5PS5162FFR-xxC H5PS5162FFR-xxI H5PS5162FFR-xxL H5PS5162FFR-xxJ [New Product] H5PS51...
Datasheet PDF File H5PS5162FFR-xxC PDF File

H5PS5162FFR-xxC
H5PS5162FFR-xxC

Overview
H5PS5162FFR Series 512Mb DDR2 SDRAM H5PS5162FFR-xxC H5PS5162FFR-xxI H5PS5162FFR-xxL H5PS5162FFR-xxJ [New Product] H5PS5162FFR-xxP H5PS5162FFR-xxQ This document is a general product description and is subject to change without notice.
Hynix Semiconductor does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
1.
1 / Sep.
2010 1 H5PS5162FFR series Revision History Rev.
1.
0 1.
1 History Release Insert DDR2-1066 & modify DDR2-800 tFAW value Draft Date Jul.
2008 Sep.
2010 Rev.
1.
1 / Sep.
2010 2 Contents 1.
Description 1.
1 Device Features and Ordering Information 1.
1.
1 Key Features 1.
1.
2 Ordering Information 1.
1.
3 Ordering Frequency 1.
2 Pin configuration 1.
3 Pin Description 2.
Maximum DC ratings 2.
1 Absolute Maximum DC Ratings 2.
2 Operating Temperature Condition 3.
AC & DC Operating Conditions 3.
1 DC Operating Conditions 5.
1.
1 Recommended DC Operating Conditions(SSTL_1.
8) 5.
1.
2 ODT DC Electrical Characteristics 3.
2 DC & AC Logic Input Levels 3.
2.
1 Input DC Logic Level 3.
2.
2 Input AC Logic Level 3.
2.
3 AC Input Test Conditions 3.
2.
4 Differential Input AC Logic Level 3.
2.
5 Differential AC output parameters 3.
3 Output Buffer Levels 3.
3.
1 Output AC Test Conditions 3.
3.
2 Output DC Current Drive 3.
3.
3 OCD default characteristics 3.
4 IDD Specifications & Measurement Conditions 3.
5 Input/Output Capacitance 4.
AC Timing Specifications 5.
Package Dimensions H5PS5162FFR series Rev.
1.
1 / Sep.
2010 3 H5PS5162FFR series 1.
Description 1.
1 Device Features & Ordering Information 1.
1.
1 Key Features • VDD ,VDDQ =1.
8 +/- 0.
1V • All inputs and outputs are compatible with SSTL_18 interface • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data Strobe (DQS, DQS) • Data outputs on DQS, DQS edges when read (edged DQ) • Data inputs on DQS centers when write(centered DQ) • On chip DLL align DQ, DQS and DQS tr...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)