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IS61NLP204836B

Part Number	IS61NLP204836B
Manufacturer	Integrated Silicon Solution
Description	PIPELINE (NO WAIT) STATE BUS SRAM
Published	Jul 25, 2016
Detailed Description	IS61NLP204836B/IS61NVP/NVVP204836B IS61NLP409618B/IS61NVP/NVVP409618B 2M x 36 and 4M x 18 JULY 2019 72Mb, PIPELINE '...
Datasheet	IS61NLP204836B PDF File

Overview

IS61NLP204836B/IS61NVP/NVVP204836B IS61NLP409618B/IS61NVP/NVVP409618B 2M x 36 and 4M x 18 JULY 2019 72Mb, PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages • Power supply: NLP: Vdd 3.
3V (± 5%), Vddq 3.
3V/2.
5V (± 5%) NVP: Vdd 2.
5V (± 5%), Vddq 2.
5V (± 5%) NVVP: Vdd 1.
8V (± 5%), Vddq 1.
8V (± 5%) • JTAG Boundary Scan for PBGA packages • Industrial temperature available • Lead-free available FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency 250 200 2.
8 3.
1 4 5 250 200 DESCRIPTION The 72 Meg product family features high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications.
They are organized as 2,096,952 words by 36 bits and 4,193,904 words by 18 bits, fabricated with ISSI's advanced CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read.
This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input.
Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH.
In this state the internal device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the ADV input.
Whe...

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IS61NLP204836B PIPELINE (NO WAIT) STATE BUS SRAM - Integrated Silicon Solution

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