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IS61DDB44M18

Integrated Silicon Solution
Part Number IS61DDB44M18
Manufacturer Integrated Silicon Solution
Description DDR-II (Burst of 4) CIO Synchronous SRAMs
Published Jul 25, 2016
Detailed Description I7D7D2DMR-bII (2M x 36 & 4M x (Burst o. f 4) CIO 18) Synchronous SRAMs A MAY 2009 Features • 2M x 36 or 4M x 18. • ...
Datasheet PDF File IS61DDB44M18 PDF File

IS61DDB44M18
IS61DDB44M18

Overview
I7D7D2DMR-bII (2M x 36 & 4M x (Burst o.
f 4) CIO 18) Synchronous SRAMs A MAY 2009 Features • 2M x 36 or 4M x 18.
• On-chip delay-locked loop (DLL) for wide data valid window.
• Common I/O read and write ports.
• Synchronous pipeline read with late write operation.
• Double data rate (DDR-II) interface for read and write input ports.
• Fixed 4-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and control registering at rising edges only.
• Two input clocks (C and C) for data output control.
• Two echo clocks (CQ and CQ) that are delivered simultaneously with data.
• +1.
8V core power supply and 1.
5, 1.
8V VDDQ, used with 0.
75, 0.
9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls, byte writes, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.
1 functions.
• Byte write capability.
• Fine ball grid array (FBGA) package - 15mm x 17mm body size - 1mm pitch - 1...


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