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IS43R32400E

Part Number	IS43R32400E
Manufacturer	Integrated Silicon Solution
Description	128Mb DDR SDRAM
Published	Jul 25, 2016
Detailed Description	IS43/46R16800E, IS43/46R32400E 4Mx32, 8Mx16 JANUARY 2014 128Mb DDR SDRAM FEATURES DEVICE OVERVIEW • VDD and VDDQ: ...
Datasheet	IS43R32400E PDF File

Overview

IS43/46R16800E, IS43/46R32400E 4Mx32, 8Mx16 JANUARY 2014 128Mb DDR SDRAM FEATURES DEVICE OVERVIEW • VDD and VDDQ: 2.
5V ± 0.
2V (-5,-6) • VDD and VDDQ: 2.
5V ± 0.
1V (-4) • SSTL_2 compatible I/O • Double-data rate architecture; two data transfers per clock cycle • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs • Differential clock inputs (CK and CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Four internal banks for concurrent operation • Data Mask for write data.
DM masks write data at both rising and falling edges of data strobe • Burst Length: 2, 4 and 8 • Burst Type: Sequential and Interleave mode • Programmable CAS latency: 2, 2.
5, 3, and 4 • Auto Refresh and Self Refresh Modes • Auto Precharge • Tras Lockout supported (trap = trcd) OPTIONS • Configuration(s): 4Mx32, 8Mx16 • Package(s): 144 Ball BGA (x32) 66-pin TSOP-II (x16) and 60 Ball BGA (x16) • Lead-free package available • Temperature Range: Commercial (0°C to +70°C) Industrial (-40°C to +85°C) Automotive, A1 (-40°C to +85°C) Automotive, A2 (-40°C to +105°C) ISSI’s 128-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle.
The 134,217,728-bit memory array is internally organized as four banks of 32Mb to allow concurrent operations.
The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts.
The programmable features of burst length, burst sequence and CAS latency enable further advantages.
The device is available in 16-bit and 32-bit data word size Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Str...

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