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ADSP-BF704

Analog Devices
Part Number ADSP-BF704
Manufacturer Analog Devices
Description Blackfin+ Core Embedded Processor
Published Jul 26, 2016
Detailed Description Blackfin+ Core Embedded Processor ADSP-BF700/701/702/703/704/705/706/707 FEATURES Blackfin+ core with up to 400 MHz pe...
Datasheet PDF File ADSP-BF704 PDF File

ADSP-BF704
ADSP-BF704


Overview
Blackfin+ Core Embedded Processor ADSP-BF700/701/702/703/704/705/706/707 FEATURES Blackfin+ core with up to 400 MHz performance Dual 16-bit or single 32-bit MAC support per cycle 16-bit complex MAC and many other instruction set enhancements Instruction set compatible with previous Blackfin products Low-cost packaging 88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm),  RoHS compliant 184-Ball CSP_BGA package (12 mm × 12 mm × 0.
8 mm pitch), RoHS compliant Low system power with < 100 mW core domain power at 400 MHz (< 0.
25 mW/MHz) at 25°C TJUNCTION PERIPHERALS FEATURES See Figure 1, Processor Block Diagram and Table 1, Processor Comparison MEMORY 136 kB L1 SRAM with multi-parity-bit protection  (64 kB instruction, 64 kB data, 8 kB scratchpad) Large on-chip L2 SRAM with ECC protection 256 kB, 512 kB, 1 MB variants On-chip L2 ROM (512 kB) L3 interface (CSP_BGA only) optimized for lowest system power, providing 16-bit interface to DDR2 or LPDDR DRAM devices (up to 200 MHz) Security and one-time-programmable memory Crypto hardware accelerators Fast secure boot for IP protection memDMA encryption/decryption for fast run-time security EMULATOR TEST & CONTROL PLL & POWER MANAGEMENT FAULT MANAGEMENT SYSTEM CONTROL BLOCKS EVENT CONTROL WATCHDOG PERIPHERALS 1× TWI 8× TIMER 1× COUNTER B 136K BYTE PARITY BIT PROTECTED L1 SRAM INSTRUCTION/DATA L2 MEMORY 512K BYTE ROM UP TO 1M BYTE SRAM ECC-PROTECTED (& DMA MEMORY PROTECTION) EXTERNAL BUS INTERFACES MEMORY PROTECTION DYNAMIC MEMORY CONTROLLER SYSTEM FABRIC OTP MEMORY HARDWARE FUNCTIONS ANALOG SUB SYSTEM SYSTEM PROTECTION CRYPTO ENGINE (SECURITY) HADC 2× CAN 2× UART SPI HOST PORT 2x QUAD SPI 1x DUAL SPI GPIO 2× SPORT 1× MSI (SD/SDIO) 1× PPI STATIC MEMORY CONTROLLER 3× MDMA STREAMS 2× CRC 1× RTC LPDDR DDR2 16 1× USB 2.
0 HS OTG Figure 1.
Processor Block Diagram Blackfin+ is a trademark of Analog Devices, Inc.
; Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev.
A ...


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