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54F219

National Semiconductor
Part Number 54F219
Manufacturer National Semiconductor
Description 64-Bit Random Access Memory
Published Aug 5, 2016
Detailed Description Obsolete 54F 74F219 64-Bit Random Access Memory with TRI-STATE Outputs November 1994 54F 74F219 64-Bit Random Access ...
Datasheet PDF File 54F219 PDF File

54F219
54F219

Overview
Obsolete 54F 74F219 64-Bit Random Access Memory with TRI-STATE Outputs November 1994 54F 74F219 64-Bit Random Access Memory with TRI-STATE Outputs General Description The ’F219 is a high-speed 64-bit RAM organized as a 16-word by 4-bit array Address inputs are buffered to minimize loading and are fully decoded on-chip The outputs are TRI-STATE and are in the high-impedance state whenever the Chip Select (CS) input is HIGH The outputs are active only in the Read mode This device is similar to the ’F189 but features non-inverting rather than inverting data outputs Features Y TRI-STATE outputs for data bus applications Y Buffered inputs minimize loading Y Address decoding on-chip Y Diode clamped inputs minimize ringing Y Available in SOIC (300 mil only) Commercial 74F219PC 74F219SC (Note 1) 74F219SJ (Note 1) Military 54F219DL (Note 2) 54F219FL (Note 2) 54F219LL (Note 2) Package Number N16E J16A M16B M16D W16A E20A Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 300 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DLQB FLQB and LLQB Logic Symbol Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9500–1 TL F 9500 – 2 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9500 TL F 9500 – 3 RRD-B30M105 Printed in U S A Obsolete Unit Loading Fan Out Pin Names Description A0 – A3 CS WE D0 – D3 O0 – O3 Address Inputs Chip Select Input (Active LOW) Write Enable Input (Active LOW) Data Inputs TRI-STATE Data Outputs 54F 74F UL HIGH LOW 10 10 10 20 10 10 10 10 150 40 (33 3) Input IIH IIL Output IOH IOL 20 mA b0 6 mA 20 mA b1 2 mA 20 mA b0 6 mA 20 mA b0 6 mA b3 mA...


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