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54F280

National Semiconductor
Part Number 54F280
Manufacturer National Semiconductor
Description 9-Bit Parity Generator/Checker
Published Aug 5, 2016
Detailed Description 54F 74F280 9-Bit Parity Generator Checker Obsolete August 1995 54F 74F280 9-Bit Parity Generator Checker General Des...
Datasheet PDF File 54F280 PDF File

54F280
54F280


Overview
54F 74F280 9-Bit Parity Generator Checker Obsolete August 1995 54F 74F280 9-Bit Parity Generator Checker General Description The ’F280 is a high-speed parity generator checker that accepts nine bits of input data and detects whether an even or an odd number of these inputs is HIGH If an even number of inputs is HIGH the Sum Even output is HIGH If an odd number is HIGH the Sum Even output is LOW The Sum Odd output is the complement of the Sum Even output Features Y Guaranteed 4000V minimum ESD protection Commercial 74F280PC 74F280SC (Note 1) 74F280SJ (Note 1) Military 54F280DM (Note 2) 54F280FM (Note 2) 54F280LM (Note 2) Package Number N14A J14A M14A M14D W14B E20A Package Description 14-Lead (0 300 Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0 150 Wide) Molded Small Outline JEDEC 14-Lead (0 300 Wide) Molded Small Outline EIAJ 14-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9512–3 IEEE IEC TL F 9512 – 1 TL F 9512 – 2 TL F 9512–5 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9512 RRD-B30M115 Printed in U S A Unit Loading Fan Out Pin Names Description I0 – I8 RO RE Data Inputs Odd Parity Output Even Parity Output 54F 74F UL HIGH LOW 10 10 50 33 3 50 33 3 Input IIH IIL Output IOH IOL 20 mA b0 6 mA b1 mA 20 mA b1 mA 20 mA Truth Table Logic Diagram Number of HIGH Inputs I0 – I8 02468 13579 H e HIGH Voltage Level L e LOW Voltage Level Outputs R Even R Odd HL LH Obsolete TL F 9512 – 4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 Obsolete Absolute Maximum Ratings (Note ...



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