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74HCU04BQ-Q100

NXP
Part Number 74HCU04BQ-Q100
Manufacturer NXP
Description Hex unbuffered inverter
Published Sep 1, 2016
Detailed Description 74HCU04-Q100 Hex unbuffered inverter Rev. 2 — 22 October 2015 Product data sheet 1. General description The 74HCU04-Q...
Datasheet PDF File 74HCU04BQ-Q100 PDF File

74HCU04BQ-Q100
74HCU04BQ-Q100


Overview
74HCU04-Q100 Hex unbuffered inverter Rev.
2 — 22 October 2015 Product data sheet 1.
General description The 74HCU04-Q100 is a hex unbuffered inverter.
Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
2.
Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Complies with JEDEC standard JESD7A  Balanced propagation delays  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  Multiple package options 3.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name Description 74HCU04D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.
9 mm 74HCU04PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.
4 mm 74HCU04BQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.
5  3  0.
85 mm Version SOT108-1 SOT402-1 SOT762-1 NXP Semiconductors 4.
Functional diagram 74HCU04-Q100 Hex unbuffered inverter 1 1A 3 2A 5 3A 9 4A 11 5A 13 6A 1Y 2 2Y 4 3Y 6 4Y 8 5Y 10 6Y 12 mna342 Fig 1.
Logic symbol 1 12 1 34 1 56 1 98 1 11 10 1 13 12 mna343 Fig 2.
IEC logic symbol 5.
Pinning information AY mna045 Fig 3.
Logic diagram (one inverter) +&84 $  <  $  <  $  <  *1'   9&&  $  <  $  <  $  < DDD Fig 4.
Pin configuration SO14 and TSSOP14 +&84  $  9&& WHUPLQDO LQGH[DUHD <  $  <  $  <  9&&   $  <  $  <  $ *1'  <  DDD 7UDQVSDUHQWWRSYLHZ (1) This is ...



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