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UT54ACTS132

Aeroflex Circuit Technology
Part Number UT54ACTS132
Manufacturer Aeroflex Circuit Technology
Description Quadruple 2-Input NAND Schmitt Triggers
Published Sep 23, 2016
Detailed Description Standard Products UT54ACS132/UT54ACTS132 Quadruple 2-Input NAND Schmitt Triggers Datasheet November 2010 www.aeroflex.co...
Datasheet PDF File UT54ACTS132 PDF File

UT54ACTS132
UT54ACTS132

Overview
Standard Products UT54ACS132/UT54ACTS132 Quadruple 2-Input NAND Schmitt Triggers Datasheet November 2010 www.
aeroflex.
com/logic FEATURES ‰ 1.
2μ CMOS (ACTS 132) and 0.
6μ CRH CMOS process (ACS132) - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 14-pin DIP (not available for the ACS132) - 14-lead flatpack ‰ UT54ACS132 - SMD 5962-96542 ‰ UT54ACTS132 - SMD 5962-96543 DESCRIPTION The UT54ACS132 and the UT54ACTS132 are 2-input NAND gates with Schmitt Trigger input levels.
A high applied on both the inputs forces the output to a low state.
The devices are characterized over full military temperature range of -55°C to +125°C.
FUNCTION TABLE INPUTS OUTPUT An Bn Yn L LH L HH HLH HH L LOGIC SYMBOL (1) A1 (2) B1 (4) A2 (5) B2 (9) A3 (10) B3 (12) A4 (13) B4 & (3) Y1 (6) Y2 (8) Y3 (11) Y4 Note: 1.
Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12.
PINOUTS A1 B1 Y1 A2 B2 Y2 VSS 14-Pin DIP Top View A1 1 14 VDD B1 2 13 B4 Y1 3 12 A4 A2 4 11 Y4 B2 5 10 B3 Y2 6 9 A3 VSS 7 8 Y3 14-Lead Flatpack Top View 1 14 2 13 3 12 4 11 5 10 69 78 LOGIC DIAGRAM A1 B1 A2 B2 A3 B3 A4 B4 Y1 Y2 Y3 Y4 1 VDD B4 A4 Y4 B3 A3 Y3 OPERATIONAL ENVIRONMENT1 PARAMETER Total Dose SEU Threshold 2 SEL Threshold Neutron Fluence LIMIT 1.
0E6 (ACTS132) 5.
0E5 (ACS132) 80 120 1.
0E14 UNITS rads(Si) MeV-cm2/mg MeV-cm2/mg n/cm2 Notes: 1.
Logic will not latchup during radiation exposure within the limits defined in the table.
2.
Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.
3 to 7.
0 V VI/O TSTG TJ TLS ΘJC II Voltage any pin Storage Temperature range Maximum junction temperature Lead temperature (soldering 5 seconds) Thermal resistance junction to case DC input current -.
3 to VDD +.
3 -65 to +150 +175 +300 20 ±10 V °C °C °C °C/W mA PD Maximum power dissipation 1W Note: 1.
Stresses outs...


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