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CY62162GE

Cypress
Part Number CY62162GE
Manufacturer Cypress
Description 16-Mbit (512K x 32) Static RAM
Published Oct 2, 2016
Detailed Description CY62162G/CY62162GE MoBL 16-Mbit (512K × 32) Static RAM with Error-Correcting Code (ECC) 16-Mbit (512K × 32) Static RAM ...
Datasheet PDF File CY62162GE PDF File

CY62162GE
CY62162GE

Overview
CY62162G/CY62162GE MoBL 16-Mbit (512K × 32) Static RAM with Error-Correcting Code (ECC) 16-Mbit (512K × 32) Static RAM with Error-Correcting Code (ECC) Features ■ Ultra-low standby power ❐ Typical standby current: 5.
5 A ❐ Maximum standby current: 16 A ■ High speed: 45 ns/55 ns ■ Embedded error-correcting code (ECC) for single-bit error correction ■ Wide voltage range: 1.
65 V to 2.
2 V, 2.
2 V to 3.
6 V ■ 1.
0-V data retention ■ Transistor-transistor logic (TTL) compatible inputs and outputs ■ ERR pin to indicate 1-bit error detection and correction ■ Easy memory expansion with CE1 and CE2 features ■ Available in Pb-free 119-ball PBGA package, 512K × 32 bits SRAM Functional Description The CY62162G and CY62162GE devices are high performance CMOS MoBL SRAM organized as 512K words by 32-bits.
Both CY62162G and CY62162GE are available with dual chip enables.
CY62162GE includes an error indication pin that signals the host processor in the case of a single bit error-detection and correction event.
It is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones.
The device also has an automatic power down feature that reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW or BA-D HIGH).
The input and output pins (I/O0 through I/O31) are placed in a high impedance state when deselected (CE1 HIGH or CE2 LOW) or outputs are disabled (OE HIGH) or the byte selects are disabled (BA-D HIGH).
To write to the device, take chip enables (CE1 LOW, CE2 HIGH) and write enable (WE) input LOW.
If byte enable A (BA) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A18).
If byte enable B (BB) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18).
Likewise, BC and BD correspond with t...


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