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CY7C1371S

Part Number	CY7C1371S
Manufacturer	Cypress
Description	18-Mbit (512K x 36) Flow-Through SRAM
Published	Oct 2, 2016
Detailed Description	CY7C1371S 18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ Architecture 18-Mbit (512K × 36) Flow-Through SRAM with NoBL...
Datasheet	CY7C1371S PDF File

Overview

CY7C1371S 18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ Architecture 18-Mbit (512K × 36) Flow-Through SRAM with NoBL™ Architecture Features ■ No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133-MHz bus operations with zero wait states ■ Data is transferred on every clock ■ Pin-compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte Write capability ■ 3.
3 V/2.
5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 6.
5 ns (for 133-MHz device) ■ Clock Enable (CEN) pin to enable clock and suspend operation ■ Synchronous self-timed writes ■ Asynchronous Output Enable ■ Available in JEDEC-standard Pb-free 100-pin TQFP, and non Pb-free 119-ball BGA ■ Three chip enables for simple depth expansion ■ Automatic Power down feature available using ZZ mode or CE deselect ■ IEEE 1149.
1 JTAG-Compatible Boundary Scan ■ Burst Capability – linear or interleaved burst order ■ Low standby power Functional Description The CY7C1371S is a 3.
3 V, 512K × 36 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion.
The CY7C1371S is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled by the rising edge of the clock.
The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.
5 ns (133-MHz device).
Write operations are controlled by the two or four Byte Write Select (BWX) and a ...

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