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CY7C1462SV25

Part Number	CY7C1462SV25
Manufacturer	Cypress
Description	36-Mbit (1M x 36/2M x 18) Pipelined SRAM
Published	Oct 2, 2016
Detailed Description	CY7C1460SV25 CY7C1462SV25 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Pi...
Datasheet	CY7C1462SV25 PDF File

Overview

CY7C1460SV25 CY7C1462SV25 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture Features ■ Pin compatible and functionally equivalent to ZBT™ ■ Supports 250-MHz bus operations with zero wait states ❐ Available speed grades are 250 and 167 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully registered (inputs and outputs) for pipelined operation ■ Byte Write capability ■ 2.
5-V core power supply ■ 2.
5-V I/O power supply ■ Fast clock-to-output times ❐ 2.
6 ns (for 250-MHz device) ■ Clock Enable (CEN) pin to suspend operation ■ Synchronous self-timed writes ■ CY7C1460SV25 available in JEDEC-standard Pb-free 100-pin TQFP package and non Pb-free 165-ball FBGA package.
CY7C1462SV25 available in Pb-free 100-pin TQFP package ■ IEEE 1149.
1 JTAG-Compatible Boundary Scan ■ Burst capability – linear or interleaved burst order ■ “ZZ” Sleep Mode option and Stop Clock option Functional Description The CY7C1460SV25/CY7C1462SV25 are 2.
5 V, 1M × 36/2M × 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL logic, respectively.
They are designed to support unlimited true back to back Read/Write operations with no wait states.
The CY7C1460SV25/CY7C1462SV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.
This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions.
CY7C1460SV25/CY7C1462SV25 are pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by the rising edge of the clock.
All data outputs pass through output registers controlled by the rising edge of the clock.
The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.
Write operations are contr...

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CY7C1462SV25 36-Mbit (1M x 36/2M x 18) Pipelined SRAM - Cypress

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