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UT54ACS630

Aeroflex Circuit Technology
Part Number UT54ACS630
Manufacturer Aeroflex Circuit Technology
Description RadHard EDAC
Published Oct 4, 2016
Detailed Description Standard Products UT54ACS630 RadHard EDAC Datasheet May 16, 2012 www.aeroflex.com/radhard FEATURES  DC operating volta...
Datasheet PDF File UT54ACS630 PDF File

UT54ACS630
UT54ACS630

Overview
Standard Products UT54ACS630 RadHard EDAC Datasheet May 16, 2012 www.
aeroflex.
com/radhard FEATURES  DC operating voltage range 4.
5V to 5.
5V  Input logic levels - VIL = 30% of VCC - VIH = 70% of VCC  Fast propagation delay 11ns (max)  m Commercial RadHardTM CMOS - Total dose: 100K rad(Si) - Single Event Latchup immune - SEU Onset LET: >108 MeV-cm2/mg  Standard Microcircuit Drawing 5962-06239 - QML Q and V  Package: - 28-lead flatpack DESCRIPTION The UT54ACS630 is a RadHard 16-bit parallel error detection and correction circuit.
It uses a modified Hamming code to generate a 6-bit checkword from each 16-bit data word.
The checkword is stored with the data word during a memory write cycle; during a memory read cycle a 22-bit word is taken from memory and checked for errors.
Single bit errors in the data words are flagged and corrected.
Single bit errors in the checkword are flagged, but not corrected.
The position of the incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome code which is output during the error correction cycle.
PIN DESCRIPTION Pin Names Description S0, S1 Mode Control Inputs DBn Bidirectional Data Bus CBn Bidirectional Checkbit Bus SEF Single Error Flag Output DEF Double Error Flag Output DEF DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 VSS 28-Lead Flatpack Top View 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VDD SEF S1 S0 CB0 CB1 CB2 CB3 CB4 CB5 DB15 DB14 DB13 DB12 1 FUNCTION TABLES CONTROL FUNCTIONS Memory Cycle WRITE READ Control S1 S0 Low Low Low High READ READ High High High Low EDAC Function Generates Checkword Read Data and Checkword Latch and Flag Error Correct Data Word and Generate Syndrome Bits Data I/O Input Data Input Data Latch Data Output Correction Data Checkword Output Checkword Input Checkword Error Flags SEF DEF Low Low Low Low Latch Checkword Output Syndrome Bits Enabled Enabled Enabled Enabled CHECKWORD GENERATION Check word bit CB0 CB1 ...


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