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H5PS1G63KFR-xxJ

Part Number	H5PS1G63KFR-xxJ
Manufacturer	hynix
Description	1Gb DDR2 SDRAM
Published	Oct 5, 2016
Detailed Description	1Gb DDR2 SDRAM 1Gb DDR2 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5PS1G63KFR-xxC H5PS1G63KFR-xxI H5PS1G63KFR-xxJ H5...
Datasheet	H5PS1G63KFR-xxJ PDF File

Overview

1Gb DDR2 SDRAM 1Gb DDR2 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5PS1G63KFR-xxC H5PS1G63KFR-xxI H5PS1G63KFR-xxJ H5PS1G63KFR-xxL * SK Hynix reserves the right to change products or specifications without notice.
Rev.
1.
1 / Mar.
2014 1 Revision Details Rev.
1.
0 1.
1 History Official Release Typo Correction Draft Date Oct.
2013 Mar.
2014 Remark Page11 Rev.
1.
1 / Mar.
2014 2 Contents 1.
Description 1.
1 Device Features and Ordering Information 1.
1.
1 Key Features 1.
1.
2 Ordering Information 1.
1.
3 Operating Frequency 1.
2 Pin configuration 1.
3 Pin Description 2.
Maximum DC ratings 2.
1 Absolute Maximum DC Ratings 2.
2 Operating Temperature Condition 3.
AC & DC Operating Conditions 3.
1 DC Operating Conditions 3.
1.
1 Recommended DC Operating Conditions(SSTL_1.
8) 3.
1.
2 ODT DC Electrical Characteristics 3.
2 DC & AC Logic Input Levels 3.
2.
1 Input DC Logic Level 3.
2.
2 Input AC Logic Level 3.
2.
3 AC Input Test Conditions 3.
2.
4 Differential Input AC Logic Level 3.
2.
5 Differential AC Output Parameters 3.
3 Output Buffer Levels 3.
3.
1 Output AC Test Conditions 3.
3.
2 Output DC Current Drive 3.
3.
3 OCD default characteristics 3.
4 IDD Specifications & Measurement Conditions 3.
5 Input/Output Capacitance 4.
AC Timing Specifications 5.
Package Dimensions Rev.
1.
1 / Mar.
2014 3 1.
Description 1.
1 Device Features & Ordering Information 1.
1.
1 Key Features • VDD = 1.
8 +/- 0.
1V • VDDQ = 1.
8 +/- 0.
1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS) • Differential Data Strobe (DQS, DQS) • Data outputs on DQS, DQS edges when read (edged DQ) • Data inputs on DQS centers when write (centered DQ) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM mask write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and...

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