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GS81302R08GE Datasheet PDF


Part Number GS81302R08GE
Manufacturer GSI Technology
Title 144Mb SigmaDDR-II Burst of 4 SRAM
Description Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R/W Synchronous Read/Write Input Read: Active High Write: A...
Features
• Simultaneous Read and Write SigmaDDR™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/
  –100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined...

File Size 460.25KB
Datasheet GS81302R08GE PDF File








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GS81302R08E : Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R/W Synchronous Read/Write Input Read: Active High Write: Active Low BW0–BW3 Synchronous Byte Writes Input Active Low x18/x36 only NW0–NW1 Nybble Write Control Pin Input Active Low x8 only LD Synchronous Load Pin Input Active Low K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — MCL Must .

GS81302R09E : Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R/W Synchronous Read/Write Input Read: Active High Write: Active Low BW0–BW3 Synchronous Byte Writes Input Active Low x18/x36 only NW0–NW1 Nybble Write Control Pin Input Active Low x8 only LD Synchronous Load Pin Input Active Low K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — MCL Must .

GS81302R09GE : Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R/W Synchronous Read/Write Input Read: Active High Write: Active Low BW0–BW3 Synchronous Byte Writes Input Active Low x18/x36 only NW0–NW1 Nybble Write Control Pin Input Active Low x8 only LD Synchronous Load Pin Input Active Low K Input Clock Input Active High K Input Clock Input Active Low C Output Clock Input Active High C Output Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — MCL Must .




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