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GS8342DT11BD Datasheet PDF


Part Number GS8342DT11BD
Manufacturer GSI Technology
Title 36Mb SigmaQuad-II+ Burst of 4 SRAM
Description Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write I...
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) ...

File Size 271.01KB
Datasheet GS8342DT11BD PDF File








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GS8342DT10BD : Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0–BW3 Synchronous Byte Writes Input Active Low NW0–NW1 Synchronous Nybble Writes Input Active Low (x8 only) K Input Clock Input Active High K Input Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — Qn Synchronous Data Outputs Output — Dn Synchronous Data Inputs Input — Doff Disable DLL when low Input Active Low CQ O.

GS8342DT10BGD : Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0–BW3 Synchronous Byte Writes Input Active Low NW0–NW1 Synchronous Nybble Writes Input Active Low (x8 only) K Input Clock Input Active High K Input Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — Qn Synchronous Data Outputs Output — Dn Synchronous Data Inputs Input — Doff Disable DLL when low Input Active Low CQ O.

GS8342DT11BGD : Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0–BW3 Synchronous Byte Writes Input Active Low NW0–NW1 Synchronous Nybble Writes Input Active Low (x8 only) K Input Clock Input Active High K Input Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — Qn Synchronous Data Outputs Output — Dn Synchronous Data Inputs Input — Doff Disable DLL when low Input Active Low CQ O.

GS8342DT19BD : Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0–BW3 Synchronous Byte Writes Input Active Low NW0–NW1 Synchronous Nybble Writes Input Active Low (x8 only) K Input Clock Input Active High K Input Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — Qn Synchronous Data Outputs Output — Dn Synchronous Data Inputs Input — Doff Disable DLL when low Input Active Low CQ O.

GS8342DT19BGD : Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0–BW3 Synchronous Byte Writes Input Active Low NW0–NW1 Synchronous Nybble Writes Input Active Low (x8 only) K Input Clock Input Active High K Input Clock Input Active Low TMS Test Mode Select Input — TDI Test Data Input Input — TCK Test Clock Input Input — TDO Test Data Output Output — VREF HSTL Input Reference Voltage Input — ZQ Output Impedance Matching Input Input — Qn Synchronous Data Outputs Output — Dn Synchronous Data Inputs Input — Doff Disable DLL when low Input Active Low CQ O.




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