DatasheetsPDF.com

IS61VPS12836EC

Part Number	IS61VPS12836EC
Manufacturer	ISSI
Description	SINGLE CYCLE DESELECT SRAM
Published	Nov 7, 2016
Detailed Description	IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC 128K x36/32 ...
Datasheet	IS61VPS12836EC PDF File

Overview

IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC 128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM APRIL 2017 FEATURES  Internal self-timed write cycle  Individual Byte Write Control and Global Write  Clock controlled, registered address, data and control  Burst sequence control using MODE input  Three chip enable option for simple depth expansion and address pipelining  Common data inputs and data outputs  Auto Power-down during deselect  Single cycle deselect  Snooze MODE for reduced-power standby  JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages  Power supply: LPS: VDD 3.
3V (± 5%), VDDQ 3.
3V/2.
5V (± 5%) VPS: VDD 2.
5V (± 5%), VDDQ 2.
5V (± 5%)  JTAG Boundary Scan for BGA packages  Industrial and Automotive temperature support  Lead-free available  Error Detection and Error Correction FAST ACCESS TIME Symbol tKQ tKC fMAX Parameter Clock Access Time Cycle time Frequency DESCRIPTION The 4Mb product family features high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.
The IS61(64)LPS/VPS12836EC are organized as 131,072 words by 36bits.
The IS61(64)LPS/VPS12832EC are organized as 131,072 words by 32bits.
The IS61(64)LPS/VPS25618EC are organized as 262,144 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled by a positiveedge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input.
Write cycles can be one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte write en...

Similar Datasheet

IS61VPS12836A 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM - Integrated Silicon Solution
IS61VPS12836EC SINGLE CYCLE DESELECT SRAM - ISSI

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)