DatasheetsPDF.com

NB3L8543S

ON Semiconductor
Part Number NB3L8543S
Manufacturer ON Semiconductor
Description 2.5V/3.3V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs
Published Nov 23, 2016
Detailed Description NB3L8543S 2.5 V/3.3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs with Clock Enable and Clock Select Des...
Datasheet PDF File NB3L8543S PDF File

NB3L8543S
NB3L8543S

Overview
NB3L8543S 2.
5 V/3.
3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs with Clock Enable and Clock Select Description The NB3L8543S is a high performance, low skew 1−to−4 LVDS Clock Fanout Buffer.
The NB3L8543S features a multiplexed input which can be driven by either a differential or single−ended input to allow for the distribution of a lower speed clock along with the high speed system clock.
The CLK_SEL pin will select the differential CLK and CLK inputs when LOW (or left open and pulled LOW by the internal pull−down resistor).
When CLK_SEL is HIGH, the differential PCLK and PCLK inputs are selected.
The common clock enable pin, CLK_EN, is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse on the outputs during asynchronous assertion/deassertion of the clock enable pin.
The internal flip flop is clocked on the falling edge of the input clock; therefore, all...


Similar Datasheet


Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)