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MC54F109

Part Number	MC54F109
Manufacturer	Motorola
Description	DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
Published	Dec 1, 2016
Detailed Description	DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC54/74F109 consists of two high-speed, completely independent transition ...
Datasheet	MC54F109 PDF File

Overview

DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-flops.
The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to F74 data sheet) by connecting the J and K inputs together.
CONNECTION DIAGRAM VCC CD2 J2 K2 CP2 SD2 Q2 Q2 16 15 14 13 12 11 10 9 CD J K CP SD Q Q CD1 J1 K1 CP1 SD1 Q1 Q1 12 CD1 J1 3456 K1 CP1 SD1 Q1 78 Q1 GND FUNCTION TABLE (Each Half) Input Output @ tn JK @ tn + 1 QQ LH No Change LL LH HH HL HL Toggles Asynchronous Inputs: LOW Input to SD sets Q to HIGH level LOW Input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH H = HIGH Voltage Level L = LOW Voltage Level tn = Bit time before clock pulse tn + 1 = Bit time after clock pulse MC54/74F109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP FAST™ SCHOTTKY TTL 16 1 16 ...

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