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CD40102BMS

Part Number	CD40102BMS
Manufacturer	Intersil Corporation
Description	CMOS 8-Stage Presettable Synchronous Down Counters
Published	Mar 23, 2005
Detailed Description	CD40102BMS CD40103BMS December 1992 CMOS 8-Stage Presettable Synchronous Down Counters Description CD40102BMS and CD401...
Datasheet	CD40102BMS PDF File

Overview

CD40102BMS CD40103BMS December 1992 CMOS 8-Stage Presettable Synchronous Down Counters Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero.
The CD40102BMS is conﬁgured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter.
Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously.
All control inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic.
In normal operation, the counter is decremented by one count on each positive transition of the CLOCK.
Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE) inputs is high.
The CARRY-OUT/ZERO-DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period.
When the SYNCHRONOUS PRESET-ENABLE (SPE) input is low, data at the JAM input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input.
When the ASYNCHRONOUS PRESETENABLE (APE) input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE, CI/CE, or CLOCK inputs.
JAM inputs J0-J7 represent two 4-bit BCD words for the CD40102BMS and a single 8-bit binary word for the CD40103BMS.
When the CLEAR (CLR) input is low, the counter is asynchronously cleared to its maximum count (9910 for the CD40102BMS and 25510 for the CD40103BMS) regardless of the state of any other input.
The precedence relationship between control inputs is indicated in the truth table.
If all control inputs except CI/CE are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long.
This causes the CO/ZD output to go low to enable the clock on each succeeding clock pulse.
CD40102BMS, CD...

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